Present semiconductor wafers are generally circular in shape, and have one or more "flats" along their edge or periphery. The flats serve at least two purposes. First, the number and orientation of flats relative to one another indicates whether a given wafer has been inherently doped with a p-type or an n-type conductivity impurity. Second, the position of the flats is of critical importance for proper wafer alignment for the various processing steps conducted upon the wafer. Each deposition or treatment of a wafer must be specifically conducted relative to previous processing steps and wafer orientation. The flats are utilized to precisely orient the wafer in given separate processing steps to assure the most precise wafer configuration. In the context of this document, wafer flats are generically referred to as defining an orientation edge discontinuity shape. Orientation edge discontinuity includes other shapes of, for example, a general male or female configuration. A wafer flat is considered as a female configuration, as wafer edge material has been removed to provide an indentation relative to the normal circular circumference of the wafer. Other female indentations, for example V-shaped or box-shaped, might be utilized. Additionally, male projections from the circumferential edge also would constitute an orientation edge discontinuity. In the context of this document, "orientation edge discontinuity" is intended to define any peripheral exterior irregularity in shape which enables precise alignment of the wafer relative to various semiconductor processing equipment.
In semiconductor wafer processing, one common step conducted is polishing of the exposed wafer surface prior to subsequent deposition or other processing steps. This is typically accomplished to provide outer surface planarity, and also to provide electrical isolation between devices by removal of outer conductive material. One type of processing finding increasing use is chemical-mechanical polishing (CMP). A wafer carrier portion of the prior art chemical-mechanical polisher is described with reference to FIG. 1. Such constitutes an underside view of a wafer polisher apparatus indicated generally with reference numeral 10. Carrier apparatus 10 is comprised of a wafer carrier ring 12 which internally retains a wafer 14 which will be polished. Wafer 14 has an outer surface 20 which will be polished. A series of bolt holes 16 receive bolts (not shown) for mounting ring 12 to a backing plate and ultimately to a rotatable drive mechanism. The mechanism would engage ring 12 from behind and perpendicularly relative to the plane of the paper upon which FIG. 1 lies. Wafer 14 is indicated as having a particular orientation edge discontinuity shape provided by a singular female flat edge portion 18. Carrier 12 and wafer 18 would be rotatably pressed against a polishing platen (not shown) having a polishing pad supported thereatop. Ring 12 and wafer 18 would be caused to rotate, with the platen also being rotated, to produce the desired polishing action against wafer surface 20.
One goal in chemical-mechanical polishing and in other polishing is typically to produce a wafer which is substantially uniformly flat across the wafer surface. Unfortunately in chemical-mechanical polishing utilizing the FIG. 1 apparatus, this overall objective is often difficult to achieve. Typically, the portion of surface 20 being polished which is adjacent flat 18 polishes at a faster rate, and accordingly more material is removed in these locations for a given polishing step than are other portions of the wafer. The exact reasons for this phenomena are not fully understood. However, it is theorized that the polishing pad perhaps dips or extends into the illustrated open area 22 during polishing. This might result in more beating force or polishing action against those portions of the wafer adjacent flat 18 than on other portions of surface 20.
It would be desirable to overcome these and perhaps other problems associated in wafer polishing. Although the principal motivation for this invention resulted from problems associated with chemical-mechanical polishing of semiconductor wafers, the artisan will appreciate that aspects of the invention have applicability to other wafer polishing processes and apparatus. The invention is intended to be limited only by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.